FPGA Modeling of IEEE754-2008 Standard for Financial Transactions
P. Anil kumar1, V. Narasimha Nayak2, Fazal Noorbasha3
1P.Anil kumar, VLSI Research Group, Department of Electronics & Communication Engineering, KL University, Guntur, India.
2V. Narasimha Nayak, VLSI Research Group, Department of Electronics & Communication Engineering, KL University, Guntur, India.
3Fazal Noorbasha, VLSI Research Group, Department of Electronics & Communication Engineering, KL University, Guntur, India.
Manuscript received on March 12, 2013. | Revised Manuscript received on April 13, 2013. | Manuscript published on April 30, 2013. | PP: 719-723 | Volume-2, Issue-4, April 2013. | Retrieval Number: D1556042413/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Financial transactions are specified in decimal arithmetic. Until the introduction of IEEE 754-2008, specialized software hardware routines were used to perform these transactions but it incurred a penalty on performance. There is a need for accurate analysis of these solutions on representative DFP benchmarks. This Work uses a single precision evaluation of decimal numbers .In this paper we are taking decimal numbers and converting them into to normalization form and then finally to floating point in order to do our calculation like [addition, subtraction, multiplication, division] by using this method there is a scope of increasing accuracy of evaluation of decimal numbers, we also presented the performance analysis that gives the average number of cycles for common DFP operations and the total number of each DFP operation in each benchmark, and highlights the trade-offs between using 64-bit and 128-bit DFP operands for both binary and decimal significant encodings.
Keywords: Decimal Floating Point(DFP),Field Program-mable Gate arrays (FPGA), Floating Point(FP).