Network Interface Design and Implementation for NoC on FPGA with advanced Hardware and Networking Functionalities
Veeraprathap.V1, M.Nagaraja2, M.Z.Kurian3
1Mr.Veeraprathap.V, M.Tech 4 Th Semester Student, Department of E&C, SSIT, Tumkur.
2Dr. M. Nagaraja, Associate professor, Department of E&C, SSIT, Tumkur.
3Dr. M.Z. Kurian, Dean & HOD, Department of E&C, SSIT, Tumkur.
Manuscript received on May 24, 2013. | Revised Manuscript received on June 17, 2013. | Manuscript published on June 30, 2013. | PP: 325-330 | Volume-2, Issue-5, June 2013. | Retrieval Number: E1830062513/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: As we are living in a billion transistor era, the number of components on a given chip increases drastically, System on Chip (SoC) architectures become even more powerful. Key to this architecture is the ability to integrate multiple heterogeneous components into a single architecture, which requires modularity and abstraction. An integral part of this architectural design is the methods by which the various components communicate with one another. Network on Chip (NoC) architectures attempt to address these concerns by providing various component level architectures with specific interconnection network topologies and routing techniques. Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MP SoCs connected by means of general-purpose communication architectures. This paper presents the design and implementation of FPGA based Network on chip (NoC) which is scalable packet switched architecture with advanced Networking functionalities such as store & forward transmission, error management, power management and security. All these features are built on basic NI core, which includes data packetization, depacketisation, frequency conversion, data size conversion and conversion of protocols with limited circuit complexity and cost.
Keywords: Intellectual Property (IP), Multi-Processor System-on-Chip (MP SoC), Network-on-Chip (NoC), Network Interface (NI), VLSI Architecture.