Design of a Parallel Pipelined FFT Architecture For Real Valued Signals
Kiranraj A. Tank1, Pradnya P Zode2
1Kiranraj A. Tank, Electronics Department, Y.C.C.E, Nagpur, India.
2Mrs Pradnya P. Zode, Electronics Department, Y.C.C.E, Nagpur, India.
Manuscript received on January 25, 2014. | Revised Manuscript received on February 13, 2014. | Manuscript published on February 28, 2014. | PP: 75-77 | Volume-3, Issue-3, February 2014. | Retrieval Number: C2574023314/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a novel approach to design a four and eight parallel pipelined fast Fourier transform (FFT) architecture based on canonic signed digit multiplier. This approach is based on use of decimation in time algorithm which reduces the number of delay elements up to some extent compared to decimation in frequency based design. The number of delay elements required for an N point FFT architecture is N4 which is comparable to that of delay feedback schemes. The number of complex adders required is approximately 50% less than the other feedback designs. The proposed architecture can be extended to any radix 2n based FFT algorithm. This proposed architecture is based on feed forward designs and can be pipelined up to more stages to increase the throughput.
Keywords: Canonic signed digit (CSD), decimation in time (DIT), fast Fourier transform (FFT), folding.