Implementation of AES for Encryption in Vertex- 3 of FPGA Environment for Security
B. Satyanarayana1, M. Srinivasan2
1B.Satyanarayana, Department of ECE, Sri Satya Sai University of Technology and Medical Science, Sehore, Bhopal, Madhya Pradesh, India.
2Dr M. Srinivasan, Department of ECE, Sri Satya Sai University of Technology and Medical Science, Sehore, Bhopal, Madhya Pradesh, India.
Manuscript received on February 01, 2019. | Revised Manuscript received on February 14, 2019. | Manuscript published on December 30, 2019. | PP: 4954-4958 | Volume-9 Issue-2, December, 2019. | Retrieval Number: B3913129219/2019©BEIESP | DOI: 10.35940/ijeat.B3913.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Data transmission with protection is main concept which is getting demand now a days for which number of encryption of data techniques are developed and now in this paper Advanced Encryption Standard (AES) Algorithm is used and is implemented on FPGA kit using vertex-3 family. We use 128 bits consists of input, key data, output data for this design. It is called an iterative looping with replacement box, key, loop in this design for both encryption and decryption of data. We use Xilinx software platform for simulation of our design that is AES by which area utilization and throughput is increased for achieving low power consumption, high data security, reduced latency and easy architectural design. This data operation is applicable in many areas.
Keywords: AES, encryption, decryption, Latency, FPGA, Throughput.