2D And 3D Based Network On Chip For A Stream Of Data using Label Switching Technique
Mamatha N1, Sridevi S2, G Indumathi3, K Venkateswaran4
1Mamatha N, M*. Tech Student Department of E & C Engineering, CMR Institute of Technology Affiliated to Visvesvaraya Technological University, Bangalore, Karnataka, India.
2Sridevi S, PhD Scholar and Assistant Professor, Department of E & C Engineering, CMR Institute of Technology Affiliated to Visvesvaraya Technological University, Bangalore, Karnataka, India.
3Dr. G Indumathi, Professor and Head Department of E & C Engineering, CMR Institute of Technology Affiliated to Visvesvaraya Technological University, Bangalore, Karnataka, India.
4Dr. K Venkateswaran, Assoc. Professor, Department of E & C Engineering, CMR Institute of Technology Affiliated to Visvesvaraya Technological University, Bangalore, Karnataka, India.
Manuscript received on September 12, 2019. | Revised Manuscript received on October 05, 2019. | Manuscript published on October 30, 2019. | PP: 418-423 | Volume-9 Issue-1, October 2019 | Retrieval Number: A9407109119/2019©BEIESP | DOI: 10.35940/ijeat.A9407.109119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Universal interconnection networks are prime performance tailback for high performance SoCs (Systems-on-Chip). Since shrinking the size of the ICs (Integrated Circuits) is the main aim, NoC (Network-on-Chip), being a segmental and mountable design tactic is a propitious substitute to outmoded bus-mode architectures. NoC combined with 3D-Routers and label switching technique can guarantee low power consumption, QoS along with less latency. In the proposed work, 3D NoCs are proven to be more advantageous by achieving 39.9% reduction in Area, 1.7% reduction in Power Consumption, and 11.3% reduction in Memory usage.
Keywords: 2-D NoC, 3D-NoC, XILINX ISE, Data stream, Label Switching, Label Switched-NoC.