Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder
Daphni S1, Vijula Grace K S2
1Mrs. S. Daphni*, Research Scholar, Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thuckalay, India.
2Dr. K. S. Vijula Grace, Associate Professor Department of Electronics and Communication Engineering, Noorul Islam Centre for Higher Education, Thuckalay, India.
Manuscript received on September 16, 2019. | Revised Manuscript received on October 05, 2019. | Manuscript published on October 30, 2019. | PP: 3028-3031 | Volume-9 Issue-1, October 2019 | Retrieval Number: A1207109119/2019©BEIESP | DOI: 10.35940/ijeat.A1207.109119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix – Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.
Keywords: Brent Kung Adder, Carry Generation Stage, Hybrid Modular Parallel Prefix Adder, Kogge Stone Adder. Ladner Fischer Adder, Multiplex logic.