Low Power AVLS-TSPC based 2/3 Pre-Scaler
Anirvinnan P.1, Vaishnavi S Parashar2, D. Aneesh Bharadwaj3, Premananda B.S.4
1Anirvinnan P.,Pursuing undergraduate, Telecommunications Engineering, RV College of Engineering, Bengaluru, Karnataka, India.
2Vaishnavi S. Parashar, Pursuing undergraduate, Telecommunications Engineering, RV College of Engineering, Bengaluru, Karnataka, India.
3D. Aneesh Bharadwaj Pursuing undergraduate, Telecommunications Engineering, RV College of Engineering, Bengaluru, Karnataka, India.
4Dr. Premananda B.S., Associate Professor, Department of Telecommunication Engineering, RV College of Engineering, Bengaluru, India.
Manuscript received on September 23, 2019. | Revised Manuscript received on October 15, 2019. | Manuscript published on October 30, 2019. | PP: 6687-6693 | Volume-9 Issue-1, October 2019 | Retrieval Number: A1974109119/2019©BEIESP | DOI: 10.35940/ijeat.A1974.109119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.
Keywords: AVLG, AVLS, CMOS, Flip-flop, Pre-scaler, TSPC.