An Odd Parity Genertor Design Using Nano Electronics
S. Rooban1, K. Lakshmi Swathi2, Ch.Monica3, B.Shivaramakrishna4
1S. Rooban, Department of ECE, Koneru Lakshmiah Educational Foundation, Guntur (A.P), India.
2K.LakshmiSwathi, Department of ECE, Koneru Lakshmiah Educational Foundation, Guntur (A.P), India.
3Ch.Monica, Department of ECE, Koneru Lakshmiah Educational Foundation, Guntur (A.P), India.
4B.Shiva Rama Krishna, Department of ECE, Koneru Lakshmiah Educational Foundation, Guntur (A.P), India.
Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 597-601 | Volume-8 Issue-4, April 2019 | Retrieval Number: D6576048419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the growing trends of digitalized world, devices with low-power consumption has marked their importance. When we go for CMOS technology, we find many Nano-scale computing problems. In order to avoid them we go for an emerging Nano computing technology which is a Quantum -dot Cellular-automata. QCA has potential advantages like high speeds, low power dissipation and higher device densities. In this paper, a 4-bit, 8-bit, 16-bit and a 32-bit odd parity generator are proposed which are highly dense and consume low power.
Keywords: Quantum Dot Cellular Automata, Odd Parity Generator, QCA Designer, QCA Pro.
Scope of the Article: Nano electronics and Quantum Computing