Performance Evaluation of Different Topologies of SRAM and SRAM Memory Array Design at 180nm Technology
Rudresh T K1, Mallikarjun S H2, Sonu S Y3
1Rudresh T. K., Lecturer, Department of Electronics and Communication Engineering, Government Polytechnic, Kampli (Karnataka), India.
2Mallikarjun S. H., Lecturer, Department of Electronics and Communication Engineering, Government Polytechnic, Kampli (Karnataka), India.
3Sonu S Y, Department of Electronics and Communication Engineering, Siddaganga Institute of Technology, Tumakuru (Karnataka), India.
Manuscript received on 27 December 2022 | Revised Manuscript received on 31 December 2022 | Manuscript Accepted on 15 February 2023 | Manuscript published on 28 February 2023 | PP: 1-10 | Volume-12 Issue-3, February 2023 | Retrieval Number: 100.1/ijeat.C39830212323 | DOI: 10.35940/ijeat.C3983.0212323
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Memory circuits such as static random-access memory (SRAM) and dynamic random-access memory (DRAM) form an integral part of system design and contribute significantly to system-level power consumption. Memory operating speeds and power dissipation have become important parameters due to the explosive growth of battery-operated appliances and the increased integration of circuits Hence SRAMs with different topologies are examined in terms of parameters like propagation delay, Static Noise Margin (SNM), corner analysis, and static power dissipation by simulating using versatile tool cadence virtuoso at 180nm technology. Besides, topological performance comparison, the SRAM memory array has also been illustrated from 2×2, 4×4 to 8×8, thereby verifying the read and write modes of operation of SRAM.
Keywords: Corner Analysis, Propagation delay, SNM, SRAM Memory Array, Static Power Dissipation
Scope of the Article: Performance Evaluation of Networks