Performance Analysis of Reconfigurable Heterogeneous Adder Architectures
S.Karthick1, R.S.Valarmathy2, R.Nirmalkumar3
1S. Karthick, Assistant Professor Sl.G, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
2R.S.Valarmathy, Senior Professor & Dean, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
3R.Nirmalkumar, Assistant Professor Sr.G, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
Manuscript received on 13 December 2018 | Revised Manuscript received on 22 December 2018 | Manuscript Published on 30 December 2018 | PP: 64-69 | Volume-8 Issue-2S, December 2018 | Retrieval Number: 100.1/ijeat.B10211282S18/18 ©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The computational problems are solved by adaptable fabrics. A reconfigurable fabric has attracted high priority as the complexity and throughput has increased. The problem related to a specific architecture can be effectively addressed by reconfigurable computing. Various adder structures like Carry Bypass (CBA), Carry Look-Ahead (CLA), Ripple Carry Adder (RCA) and Carry Select (CSLA) with reconfigurable architecture are designed for Field Programmable Gate Array (FPGA) application. Performance metrics like area speed and power consumption can be effectively optimized by reconfigurable architectures. More fine grained architecture with improved can be achieved using reconfiguration techniques. The proposed structures are coded in Verilog-HDL. These architectures are targeted for 65 nm technology node using Synopsis tool. The proposed technique can be extended for more complex designs with improved performance. An area reduction of 14% to 44% and power reduction of 18% to 54% has been achieved using proposed reconfigurable adder architectures.
Keywords: Fabrics, Fine Grained, Reconfiguration, Tradeoff.
Scope of the Article: High Performance Computing