FPGA Implementation of Low Power Adaptive Filter Architecture
Sajan P. Philip1, Dr. P. Sampath2, P.V. Devakumar3, S. Elango4
1Sajan P. Philip, Professor, Department of ECE, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
2Dr. P. Sampath, Professor, Department of ECE, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
3P. V. Devakumar, PG Student, Department of ECE, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
4S. Elango, Professor, Department of ECE, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
Manuscript received on 13 December 2018 | Revised Manuscript received on 22 December 2018 | Manuscript Published on 30 December 2018 | PP: 139-142 | Volume-8 Issue-2S, December 2018 | Retrieval Number: 100.1/ijeat.B10371282S18/18 ©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: We present a hardware architecture of adaptive filter for high throughput, low power and low area using distributed arithmetic (DA). Digital signal processing algorithms basically depends on a large number of multiplications and additions. Distributed arithmetic is an useful technique to perform MAC (Multiply And Accumulate), which is a very common operation in Digital Signal Processing Algorithms and also used to calculate inner product or simply MAC. This DSP multiplication is naturally both time and power consuming and also achieving high performance is one of the prime targets in DSP applications.
Keywords: Architecture Low Power Applications.
Scope of the Article: FPGAs