Superscalar Pipelined Matrix Multiplier in VHDL
S. Arulselvi1, S. Balaji2, R. Hema3
1S. Arulselvi, Department of Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
2S. Balaji, Department of Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
3R. Hema, Department of Electronics and Communication Engineering, Bharath Institute of Higher Education and Research, Chennai (Tamil Nadu), India.
Manuscript received on 14 September 2019 | Revised Manuscript received on 23 September 2019 | Manuscript Published on 10 October 2019 | PP: 278-282 | Volume-8 Issue-6S2, August 2019 | Retrieval Number: F10750886S219/19©BEIESP | DOI: 10.35940/ijeat.F1075.0886S219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Parallel processing is used by simultaneous information processing to boost the computing velocity of the computer system. Parallel processing is implemented by pipeline processing.. In this paper we presented design of a A[100][100] x B[100][100] Pipelined Matrix Multiplier and its results is stored in P[100][100] matrix. We present design and stimulate a functional Pipelined Matrix Multiplier Unit. By which we can learn about the working of Pipelined Matrix Multiplier and how pipelining works. We also get the knowledge of clock timing and learn to make a timing critical design. In this Pipelined Matrix Multiplier Unit design we use design compiler, which is a module of Synopsys tools that uses lsi_10k library and BCCOM method to synthesis the design and simulate the design through VCS compiler.
Keywords: Parallel Processing, Pipelining, Matrix Multiplier, Clock Timing, Design Area.
Scope of the Article: Signal and Speech Processing