Design and Enactment of Dynamically Reconfigurable Bus Enhanced NoC Architecture for Emerging Digital System
A. Mariyammal1, J. Rajprabha2, A. Sountharyabanu3, N. Sangavi4, G. Malarvizhi5
1A. Mariyammal, Assistant Professor, Vivekananda College of Engineering for Women Autonomous, Tiruchengode (Tamil Nadu), India.
2J. Rajprabha, UG Scholar, Vivekananda College of Engineering for Women Autonomous, Tiruchengode (Tamil Nadu), India.
3A. Sountharyabanu, UG Scholar, Vivekananda College of Engineering for Women Autonomous, Tiruchengode (Tamil Nadu), India.
4N. Sangavi, UG Scholar, Vivekananda College of Engineering for Women Autonomous, Tiruchengode (Tamil Nadu), India.
5G. Malarvizhi, UG Scholar, Vivekananda College of Engineering for Women Autonomous, Tiruchengode (Tamil Nadu), India.
Manuscript received on 30 September 2019 | Revised Manuscript received on 12 November 2019 | Manuscript Published on 22 November 2019 | PP: 1501-1504 | Volume-8 Issue-6S3 September 2019 | Retrieval Number: F12680986S319/19©BEIESP | DOI: 10.35940/ijeat.F1268.0986S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The large amount imperative issue in present VLSI circuit proposes in the area and power reduction. This work proposes a new architecture which reduces an area efficiently. The reimbursement of adding a little latency, modified mutual bus as an essential element of the NoC structural design is explored. This architecture design reduces the charge of partisan a broad choice of design occurrence through specified throughput needs by minimizing the requirement of design entities in the architecture design of NoC road and rail network for the area minimization.
Keywords: Master Memory, Slave Memory, Network Interface, Switch, Processing Element.
Scope of the Article: Digital System and Logic Design