A Modified Double-Precision Floating-Point Multiplier to Achieve Reduced Hardware Utilization
Y. Srinivasa Rao1, A. Bhanu Chandar2
1Y. Srinivasa Rao, Assistant Professor, Department of ECE, Malla Reddy Engineering College for Women Autonomous, Secunderabad (Telangana), India.
2A. Bhanu Chandar, Assistant Professor, Department of ECE, Malla Reddy Engineering College for Women Autonomous, Secunderabad (Telangana), India.
Manuscript received on 01 November 2019 | Revised Manuscript received on 13 November 2019 | Manuscript Published on 22 November 2019 | PP: 1944-1948 | Volume-8 Issue-6S3 September 2019 | Retrieval Number: F13750986S319/19©BEIESP | DOI: 10.35940/ijeat.F1375.0986S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The DP(Double-Precision) floating-point multiplier require a bulky 52×52 mantissa multiplications. The enactment of the DP floating number multiplication predominantly be influenced by on the area and speed. This paper presents a improved unique method to diminution this huge multiplication practice of mantissa. The UT method permitsusinga reduced quantity of multiplication hardware equaled to the conventional method. In old-fashioned scheme accumulation of the partial products are independently completed and it may perhap syiel dextra period of time in contrast to the suggested method. In the suggested process the partial products are parallel added with the multiplication actions and it can reduce the time delay. The method was instigated using Verilog HDL with Xilinx 14.2 ISE tools on Virtex-5 FPGA.
Keywords: DP (Double-Precision), Floating Point, Multiplication, Vedic, Urdhva Tiryagbhyam (UT), IEEE-754, Virtex-5 FPGA.
Scope of the Article: Cloud Resources Utilization in IoT