Technique to Dynamically Reconfigure FPGAs using Control Registers
Sreenath Thangarajan1, Reena Monica P.2
1Sreenath Thangarajan, SENSE, Vellore Institute of Technology, Chennai (Tamil Nadu), India.
2Reena Monica P, SENSE, Vellore Institute of Technology, Chennai (Tamil Nadu), India.
Manuscript received on 14 December 2019 | Revised Manuscript received on 22 December 2019 | Manuscript Published on 31 December 2019 | PP: 117-121 | Volume-9 Issue-1S3 December 2019 | Retrieval Number: A10241291S319/19©BEIESP | DOI: 10.35940/ijeat.A1024.1291S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Due to increased use of FPGAs computation intensive applications, the need for embedded processing system integrated with programmable logic device has also increased. Configuration of programmable logic device by the processing system through its interface improves the efficiency of the device. In order to operate as a stand-alone device and to have a better efficiency, the programmable logic device must be capable of dynamically programming its own configuration memory. In this paper, we propose a configurable logic block with a control register to improve performance of the programmable logic device. The control register acts like a decentralized configuration memory array which can be programmed by other such configurable logic blocks. The FPGAs are fault tolerant devices with repetitive structures requiring high packaging density. This property of FPGA enables the use of CNTFETs for design of FPGAs. CNTFETs offer high trans-conductance and 1-D ballistic transport of electrons and holes which minimizes the power consumed by the FPGA. The proposed control register based architecture was implemented using Cadence Virtuoso using virtual source CNTFET model from Stanford University. A power reduction of 17.62% is achieved using CNTFETs when compared with FINFET at same technology node and the architecture was verified for various configurations of the control register.
Keywords: FPGA, ARM, Control Register, Dynamic Configurability, CNTFET, CLB.
Scope of the Article: FPGAs