Merged Floating Point Multipliers
Mrudula Singamsetti1, Sadulla Shaik2, T. Pitchaiah3
1Mrudula Singamsetti, Department of Electronics & Communication Engineering, Vignan’s Foundation for Science, Technology and Research, Guntur (A.P), India.
2Sadulla Shaik, Department of Electronics & Communication Engineering, Vignan’s Foundation for Science, Technology and Research, Guntur (A.P), India.
3T.Pitchaiah, Department of Electronics & Communication Engineering, Vignan’s Foundation for Science, Technology and Research, Guntur (A.P), India.
Manuscript received on 25 November 2019 | Revised Manuscript received on 19 December 2019 | Manuscript Published on 30 December 2019 | PP: 178-182 | Volume-9 Issue-1S5 December 2019 | Retrieval Number: A10421291S52019/19©BEIESP | DOI: 10.35940/ijeat.A1042.1291S519
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.
Keywords: Floating point multiplier, Booth Multipliers, Dadda Multiplier, Resource Sharing Karatsuba Algorithm, Wallace Multiplier.
Scope of the Article: QOS And Resource Management