Deadlock Free Routing in Irregular Interconnection Networks for Complex SoCs
Naveen Choudhary
Naveen Choudhary, Department of Computer Science and Engineering, College of Technology and Engineering, MPUAT, Udaipur, India.
Manuscript received on November 15, 2011. | Revised Manuscript received on December 01, 2011. | Manuscript published on December 30, 2011. | PP: 131-136 | Volume-1 Issue-2, December 2011. | Retrieval Number: B0162121211/2011©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Networks-on-Chip (NoC) is recently proposed as an alternative communication infrastructure/Interconnection Network for address the high communication demands of the complex futuristic SoCs. Most researchers advocate the use of traditional regular networks like meshes as architectural templates which gained a high popularity in general-purpose parallel computing. However, most SoC platforms are special-purpose tailored to the domain-specific requirements of their application. They are usually built from a large diversity of heterogeneous components which communicate in a very specific, mostly irregular way. In such systems the size and nature of cores may vary quite widely making the topology irregular. Moreover regular topologies can become irregular due to faults in links and switches. In such scenario topology agnostic routing algorithms are generally required. In this paper, a survey of various deadlock free table based routing function is presented. The paper presents survey of deadlock free routing function with and without the availability of virtual layers
Keywords: Interconnection Networks, System on Chip, Routing, Deadlock, Virtual Layers