Design and Implementation of Low Power Energy Efficient Binary Coded Decimal Adder
N. Saravana Kumar2, K.N. Vijeya Kumar2, K. Sakthisudhan3, S. Saranya4
1Dr. N. Saravana Kumar, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
2Dr. K.N. Vijeya Kumar, Department of Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology Pollachi (Tamil Nadu), India.
3Dr. K. Sakthisudhan, Department of Electronics and Communication Engineering, Adhi College of Engineering and Technology Kancheepuram (Tamil Nadu), India.
4Ms. S.Saranya, Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
Manuscript received on 13 December 2018 | Revised Manuscript received on 22 December 2018 | Manuscript Published on 30 December 2018 | PP: 119-125 | Volume-8 Issue-2S, December 2018 | Retrieval Number: 100.1/ijeat.B10331282S18/18©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A novel architecture for low power decimal addition using binary representation is presented in this paper. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed adder design is done using VHDL code and implemented in Altera Quartus board. The results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison.
Keywords: Ripple Carry Adder, Constant Correction, Binary to Excess Six Conversion, Terahertz Optical Asymmetric Demultiplexer.
Scope of the Article: Low-power design