Challenges on Performance Analysis and Enhancement of Multi – Core Architecture, a Solution Parallel Programming Languages
Surendra Kumar Shukla1, Vishal Trivedi2, Ayush Choukse3
1Surendra Kumar Shukla, Department of CSE, DAVV, SCSIT, Indore, India.
2Vishal Trivedi, Department of Information Technology RGPV, University, Chemeli Devi School of Engineering Indore, India.
3Ayush Choukse, Department of CSE, RGPV, University, Chemeli Devi School of Engineering Indore, India.
Manuscript received on November 25, 2013. | Revised Manuscript received on December 15, 2013. | Manuscript published on December 30, 2013. | PP: 110-114 | Volume-3, Issue-2, December 2013. | Retrieval Number: B2388123213/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Performance of computer is major concern in computer architecture. Mores law has gone now, we can not increase the speed of single processor as it has problem of power requirement. So we need to move on multi core processors. Comiler is a main parameter who can give the deatil of parallelism on source code. In this paper we have proposed a scheme where we are utilizing the comiler for detecting and increasing the execution speed of souce code.
Keywords: Complier, Performance, Multi-core architecture.