Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor
Divya. D1, Balasaraswathi. R2, Harini kalyani. M3, Vivek Anand. I4
1D Divya, Undergraduate Student, Department of Electronics and Communication Engineering, National Engineering College, Tamil Nadu, India.
2R Balasaraswathi, Undergraduate Student, Department of Electronics and Communication Engineering, National Engineering College, Tamil Nadu, India.
3M Harini Kalyani, Undergraduate Student, Department of Electronics and Communication Engineering, National Engineering College, Tamil Nadu, India
4I. Vivek Anand, Assistant Professor, Department of Electronics and Communication Engineering National Engineering College, Kovilpatti, India.
Manuscript received on January 24, 2020. | Revised Manuscript received on February 05, 2020. | Manuscript published on February 29, 2020. | PP: 3783-3789 | Volume-9 Issue-3, February 2020. | Retrieval Number: C6203029320/2020©BEIESP | DOI: 10.35940/ijeat.C6203.029320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section comprises a double-precision floating-point multiplier designed during a corollary architecture thus improving the speed and veracity of the execution. All the sections are designed using Verilog coding. Monotonous instruction format, cognate prosaic-purpose registers, and pellucid addressing modes were the other miens. RISC exemplified as Reduced Instruction Set Computer. For designing high-performance processors, RISC is considered to be the footing. The RISC processor has a diminished number of Instructions, fixed instruction length, more prosaic-purpose register which are catalogued into the register file, load-store architecture and facilitate addressing modes which make diacritic instruction execute faster and achieve a net gain in performance. Thus the cardinal intent of this paper is to consummate the veridicality by devouring less power, area and with merest delay and it would be done by reinstating the floating-point ALU with single precision section by floating- point double precision section. Video processing, telecommunications and image processing were the high end applications used by architecture.
Keywords: Double precision , RISC, Floating –point ALU,Instruction decoder.