Implementation of GA with Position Based Crossover-PX Technique for Size Optimization of BDD Mapped Adder Circuits
M. Balal Siddiqui1, M. T. Beg2, S. N. Ahmad3
1Md Balal Siddiqui*, Department of Electronics & Communication Engineering, Jamia Millia Islamia, New Delhi, India.
2M. T. Beg, Department of Electronics & Communication Engineering, Jamia Millia Islamia, New Delhi, India.
3S. N. Ahmad, Department of Electronics & Communication Engineering, Jamia Millia Islamia, New Delhi, India.
Manuscript received on January 22, 2020. | Revised Manuscript received on February 05, 2020. | Manuscript published on February 29, 2020. | PP: 4215-4218 | Volume-9 Issue-3, February 2020. | Retrieval Number: C6358029320/2020©BEIESP | DOI: 10.35940/ijeat.C6358.029320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Binary Decision Diagrams or BDD are data structure used to represent single and multi-output digital circuits. BDD mapped adder circuits are used to represent different adder functions in a digital system. Optimization of adder circuits are done by optimizing the corresponding BDDs. In this work the optimization of BDD Mapped adder circuits are proposed by using genetic algorithm with position-based crossover-PX technique. The main feature of position-based crossover technique is that it is suitable for order-based solution formation. We compared our result with other existing variable order method available in BDD manipulation tool BuDDy-2.4. The result is obtained for Full Adder circuits of 1 to 8-bit size. Experimental results show the improvement of the proposed work over other techniques. The result is quite significant for large circuits i.e. full adder circuit having larger bit size.
Keywords: Adder, BDD, Binary Decision Diagram, Optimization, Variable Ordering.