Low Power CMOS Counter Using Clock Gated Flip-Flop
Upwinder Kaur1, Rajesh Mehra2
1Upwinder Kaur, Electronics & Communication Engineering Department, National Institute of Technical Teachers„ Training & Research, Sector-26, Chandigarh, India.
2Rajesh Mehra, Electronics & Communication Engineering Department, National Institute of Technical Teachers„ Training & Research, Sector-26, Chandigarh, India.
Manuscript received on March 12, 2013. | Revised Manuscript received on April 13, 2013. | Manuscript published on April 30, 2013. | PP: 796-798 | Volume-2, Issue-4, April 2013. | Retrieval Number: D1524042413/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The synchronous designs operates at highest frequency that derives a large load because it has to reach many sequential elements throughout the chip. Thus clock signals have been a great source of power dissipation because of high frequency and load. Clock signals do not perform any computation and mainly used for synchronization. Hence these signals are not carrying any information .So, by using clock gating one can save power by reducing unnecessary clock activities inside the gated module. A new counter using clock gated flip-flop is presented in this paper. The circuit is based on a new clock gating flip flop approach to reduce the signal’s switching power consumption. It has reduced the number of transistors. The proposed flip-flop is used to design 10 bits binary counter. This counter has been designed up to the layout level with 1V power supply in 90nm CMOS technology and have been simulated using Microwind simulations. Simulations have shown the effectiveness of the new approach on power consumption and transistor count.
Keywords: Clock gating, master- slave configuration, power consumption, and switching activity.