A Fast FPGA based Architecture Implementation for Reversible Image Watermarking
Dheeraj S. Patil1, M. V. Patil2
1Dheeraj S. Patil, Department of Electronics Engineering, Bharati Vidyapeeth Deemed University College of Engineering, Pune (Maharashtra), India.
2Prof M. V. Patil, Department of Electronics Engineering, Bharati Vidyapeeth Deemed University College of Engineering, Pune (Maharashtra), India.
Manuscript received on 15 April 2016 | Revised Manuscript received on 25 April 2016 | Manuscript Published on 30 April 2016 | PP: 228-232 | Volume-5 Issue-4, April 2016 | Retrieval Number: D4561045416/16©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Now a day’s different techniques are available for digital image watermarking including software and hardware implementation. Reversible contrast mapping (RCM) is one of the technique is used for embed secret information into the digital form. RCM algorithm is simple integer transform of the pixel pair and there LSB bits are used for data embedding. RCM offers high embedding rate, low mathematical calculation and good robustness. This paper focuses on implementation of Field Programmable Gate Array (FPGA) based fast image watermarking using RCM algorithm. The given architecture requires 52 slices, 52 number of flip-flop, 85 number of 4-input LUTs and transceiver data rate is up to 3.2Gbps with an operating crystal frequency is 100MHz. Given architecture is implemented with Xilinx 14.7 on Spartan-6 FPGA family. The given architecture is acceptable for various application areas such as digital cameras, medical and military applications, etc.
Keywords: Image Processing, RCM, FPGA
Scope of the Article: Image Processing