Optimization of CSA for Low Power and High Speed using MTCMOS and GDI Techniques 
Tulasi Radhika Patnala1, Sankararao Majji2, Gopala Krishna Pasumarthi3
1Tulasi Radhika Patnala, Department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad (Telangana), India.
2Sankararao Majji, Department of ECE, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad (Telangana), India.
3Gopala Krishna Pasumarthi, Department of IT, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad (Telangana), India.
Manuscript received on 27 August 2019 | Revised Manuscript received on 03 September 2019 | Manuscript Published on 14 September 2019 | PP: 285-288 | Volume-8 Issue-5S3, July 2019 | Retrieval Number: E10620785S319/19©BEIESP | DOI: 10.35940/ijeat.E1062.0785S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The basic operation involved in any analog, digital, control system, DSP’s is addition. Performance and reliability of almost every digital system is depends on performance of adder. Over the decade, many adder architectures are proposed and still research work is going on adder to obtain the best results in power, delay and power delay product (PDP). In this paper we proposed one of the fastest adder architecture called Carry Select adder (CSA) and optimization is done for performance parameters like delay and power using GDI (Gate Diffused Input) and MTCMOS techniques. Implementation has been done in standard gpdk 90nm technology using Cadence tool.
Keywords: Carry Select Adder, Gate Diffused Input, Power Delay Product And MTCMOS.
Scope of the Article: Low-power design