Hardware Modeling of VTD- Cache for fine Grain Voltage Scaling
Y. Ch Sekhar1, P.S. Srinivas Babu2
1Y.Ch Sekhar, Department of Electronics & Communication Engineering, K L University, Vijayawada, India.
2P.S. Srinivas Babu, Department of Electronics & Communication Engineering, K L University, Vijayawada, India.
Manuscript received on May 24, 2013. | Revised Manuscript received on June 19, 2013. | Manuscript published on June 30, 2013. | PP: 77-80 | Volume-2, Issue-5, June 2013. | Retrieval Number: E1708062513/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This proposed title of this work allows us to design Variation Trained Drowsy Cache for significant saving of power consumption. When addressing reliability issues. The novel and modular architecture of the VTD – Cache and its associated controller makes it easy to implemented in memory compilers with a small area and power overhead. With proper selection of scaled voltage levels and hort training period the proposed architecture allows micro tuning of the cache and also this architecture variation of supply voltage settings. We model this scheme on FPGA core.
Keywords: Cache, drowsy cache, static random access memory (SRAM), AXI protocol.