Review on: Low Power VLSI Design of Modified Booth Multiplier
Shweta S. Khobragade1, Swapnali P. Karmore2
1Shweta S. Khobragade, Electronics Department, G H Raisoni College Of Engineering, Nagpur, India.
2Swapnali S. Karmore, Computer Science Department, G H Raisoni College of Engineering, Nagpur, India.
Manuscript received on May 12, 2013. | Revised Manuscript received on June 13, 2013. | Manuscript published on June 30, 2013. | PP: 463-466 | Volume-2, Issue-5, June 2013. | Retrieval Number: E1861062513/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power VLSI circuits became very vital criteria for designing the energy efficient electronic designs for prime performance and compact devices. Multipliers play a very important role for planning energy economical processors that decides the potency of the processor. To scale back the facility consumption of multiplier factor booth coding methodology is being employed to rearrange the input bits. The operation of the booth decoder is to rearrange the given booth equivalent. Booth decoder can increase the range of zeros in variety. Hence the switching activity are going to be reduced that further reduces the power consumption of the design. The input bit constant determines the switching activity part that’s once the input constant is zero corresponding rows or column of the multiplier ought to be deactivated. When multiplicand contains more number of zeros the higher power reduction can takes place. So in modified booth multiplier high power reductions will be achieved.
Keywords: Digital signal processing, Carry Save Adder, Full Adder(FA),Column Bypass Multiplier (CBM).