Design of Decoders using Mixed Logic for Various Applications
Simma. Ranjitha1, Pasumarthy. Srikanth2
1Simma Ranjita, Department of Electronics and Communication Engineering, Sri Sivani institute of Technology, Srikakulam (Andhra Pradesh), India.
2P. Srikanth, Assistant Professor, Department of Electronics and Communication Engineering, MVGR College of Engineering, Vizianagaram (Andhra Pradesh), India.
Manuscript received on 10 August 2017 | Revised Manuscript received on 18 August 2017 | Manuscript Published on 30 August 2017 | PP: 43-47 | Volume-6 Issue-6, August 2017 | Retrieval Number: E5088066517/17©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, a mixed-logic design of decoders, combining modified GDI logic, transmission gate logic, and pass transistor logic has been proposed. A novel topology is presented for the 2-4 decoders: a 15- transistor topology on the intension of achieving low power and low delay. Further, three decoders 3-8, 4-16 and 5-32 are implemented by using mixed-logic 2-4 decoders. MGDI technique uses same number of transistors present in CMOS the main difference is the providing input signals to the source and gate terminals. These all proposed decoders reduce the power and delay compared to conventional CMOS decoders. The proposed 2×4 decoder is implemented to decrease power; increase the performance is used in full adder and 4×4 bit SRAM array. Finally simulations are done by using CMOS 130nm mentor graphics tool to give a significant improvement in power and delay.
Keywords: Decoders; Sense Amplifier; SRAM Cell; High Speed; Mixed Logic; MGDI Logic.
Scope of the Article: Fuzzy Logics