Reversible Vedic Multiplier
Venkata Latha.G1, Syamala.Y2, Anil Chowdary.T3, Murali Krishna. G4
1G.Venkatalatha, Department of ECE, Gudlavalleru Engineering College, Gudlavalleru (A.P), India.
2Y.Syamala, Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India.
3T. Anil Chowdary, Department of ECE, KL University, Vijayawada (A.P), India.
4G.Murali Krsihna Department of EEE, V.K.R,V.N.B &A.G.K College of Engineering, Gudivada (A.P), India.
Manuscript received on 15 September 2019 | Revised Manuscript received on 24 September 2019 | Manuscript Published on 10 October 2019 | PP: 852-857 | Volume-8 Issue-6S2, August 2019 | Retrieval Number: F12110886S219/19©BEIESP | DOI: 10.35940/ijeat.F1211.0886S219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the new era of technology speed effective advanced multiplier has greatest demand, where they acts as an essential part in almost all high speed processing units which are used currently. As the multiplier is one of the essential components in several computing machines, for instant microprocessors, DSPs (Digital Signal Processors) and quantum computational and combinational systems. The performances of different processors is measured based on number of multiplication completed per second. So efficient multiplier designs are to be found to meet these performance constraints and one such approach which provides solution to above problem is Vedic multiplier. It is simple in structure and increase the efficiency by reducing the unnecessary steps in multiplication. Furthermore, implementing the designed multiplier using reversible gates can decreases the dissipation of power also, which is another essential design constraint that to be met in an embedded system. In the present work, a 4X4 reversible Vedic multiplier is designed; moreover it can offers more efficiency in terms of reversible design parameters such as TRLIC (Total Reversible Logic Implementation Cost) and delay. Code for 4X4 Vedic multiplication operation is written using Verilog HDL programming language and simulation is done using Xilinx 14.7 ISE is targeted to selected FPGA device family as Vertex 6.
Keywords: Modified 2X2 Vedic Multiplier, Reversible Gates, Ripple Carry Adder, Vedic Multiplier.
Scope of the Article: Multi-Agent Systems