Time Amplifier Based Bang-Bang Phase Frequency Detector in 0.18μm CMOS Technology
Vikas Balikai1, Harish Kittur2
1Vikas Balikai, Research Scholar, Department of Electronics and Communication Engineering (SENSE), Vellore Institute of Technology University, Vellore (Tamil Nadu), India.
2Harish Kittur, Senior IEEE Member, and Dean, Department of Electronics and Communication Engineering (SENSE), Vellore Institute of Technology University, Vellore (Tamil Nadu), India.
Manuscript received on 14 December 2019 | Revised Manuscript received on 22 December 2019 | Manuscript Published on 31 December 2019 | PP: 85-89 | Volume-9 Issue-1S3 December 2019 | Retrieval Number: A10171291S319/19©BEIESP | DOI: 10.35940/ijeat.A1017.1291S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A CMOS Implementation of Time amplifier (TA) based Bang-Bang Phase Frequency Detector (BBPFD) using Sense amplifier based flip flop (SAFF) is presented in this paper using 0.18μm CMOS technology. A time amplifier based on feedback output generator concept is utilized in minimizing the metastability and increasing the gain of TA which in turn boosts the gain of Phase Frequency Detector (PFD). Also, a modified SAFF was built in CMOS 0.18μm technology at 1.8V which further reduces the hysteresis and metastability aspect related to PFD. The proposed PFD works at a maximum frequency of 4GHz consuming 0.46mW of power with no dead zone.
Keywords: Time Amplifier, BBPFD, SAFF.
Scope of the Article: Frequency Selective Surface