Clock Delayed Dual Keeper Domino-Logic Design with Reduced Switching
Anju Varghese1, Anusha. S.R2, A. Anita Angeline3, Kanchana Bhaaskaran.V.S4
1Anju Varghese, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
2Anusha S R, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
3A. Anita Angeline, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
4Kanchana Bhaaskaran V.S, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
Manuscript received on 18 December 2019 | Revised Manuscript received on 24 December 2019 | Manuscript Published on 31 December 2019 | PP: 397-402 | Volume-9 Issue-1S3 December 2019 | Retrieval Number: A10721291S319/19©BEIESP | DOI: 10.35940/ijeat.A1072.1291S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Clock Delayed Dual Keeper domino logic style with Static Switching mechanism (CDDK_SS) using delayed enabling of the keeper circuit and modified discharge path has been proposed in this paper. In CDDK domino circuit, the principle of delayed enabling of keeper circuit offers reduced contention between keeper circuit and Pull Down Network (PDN). The modified discharge path at the output node eradicates the switching at the output node for identical TRUE inputs during the pre-charge phase. This facilitates in obtaining static like output in contrast with conventional domino logic. The simulation results of Arithmetic and Logic Unit (ALU) subsystems demonstrate 17.7% reduction in dynamic power consumption while compared to conventional domino logic. Furthermore, 62% enhancement in speed performance has been achieved with good robustness. Design and simulation have been executed using Cadence® Virtuoso, with UMC 90nm technology node library.
Keywords: Domino logic, Keeper Transistor, Static Switching Mechanism, High Speed, Low Power Consumption.
Scope of the Article: Routing, Switching and Addressing Techniques