A Modified Fused Floating Point Three Term Adder
Neeraja P K1, Ramadass Narayanadass2
1Neeraja P K, Department of Electronics and Communication Engineering,CollegeofEngineeringGuindy,AnnaUniversity,Chennai,India.
2Ramadass Narayanadass*, Department of Electronics and Communication Engineering, College of Engineering Guindy, Anna University, Chennai, India.
Manuscript received on October 05, 2020. | Revised Manuscript received on October 10, 2020. | Manuscript published on October 30, 2020. | PP: 415-419 | Volume-10 Issue-1, October 2020. | Retrieval Number: 100.1/ijeat.A19081010120 | DOI: 10.35940/ijeat.A1908.1010120
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Abstract: This paper is about a modified architecture for a fused floating point three term adder. The important feature of a fused floating-point three-term adder is its ability to do multiple additions in same block to get better performance as well as accuracy compared to a conventional discrete floating point adder. The parallel prefix adder is one amongst the fastest adders and out of which the han-carlson adder represents a blend of the kogge-stone adders and brent-kung adder. In this work, han carlson adder is used to enhance the performance of the three term adder along with various optimization techniques. The adder is implemented using Verilog language in Xilinx ISE Design suite 14.2 and all Simulations are carried out in Isim simulator. Synthesis is done using Cadencetool.
Keywords: Floating point adder, Parallel prefix addition, Kogge Stone adder, Han Carlson adder.