Integrating a PCI IP Core to FPGA- Design and Implementation
G.Prasad1, N.Vasantha2
1G.Prasad, Scientist SF, National Remote Sensing Centre, Isro, Hyderabad, India.
2N.Vasantha, Professor & Head, Department of Information Technology, Vasavi College of Engineering, Hyderabad, India.
Manuscript received on September 24, 2013. | Revised Manuscript received on October 17, 2013. | Manuscript published on October 30, 2013. | PP: 36-40 | Volume-3, Issue-1, October 2013. | Retrieval Number: A2141103113/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: High volume and high throughput rates are the need for high speed data acquisition applications. Higher efficiency and throughput is achieved by the pci bus technology. By becoming a part of the plug & play domain of the host’s operating system, no additional data transfer protocols are needed. In this paper we have used a high density field- programmable gate array (FPGA) logic along with PCI master core for high data rate data acquisition. An FPGA with embedded PCI master core serves as a programmable interface between PCI bus and a local FIFO. The application dependent controller functions as well as FIFO and PCI interfacing are handled by FPGA logic. A Linux driver was developed to interface with the core in the FPGA and achieve high bandwidth in DMA mode. This paper will first provide an overview of IP use, including the advantages and disadvantages of using IP. The use of IP will be considered from the view of satellite ground reception applications.
Keywords: Data Acquisition buses, PCI bus, DMA transactions, FIFO read out.