Design of MIPS based 64-bit RISC Processor
G. Jhansi
G. Jhansi, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Education Society’s Group of Institutions, Chowdariguda (Telangana), India.
Manuscript received on 10 October 2017 | Revised Manuscript received on 18 October 2017 | Manuscript Published on 30 October 2017 | PP: 48-51 | Volume-7 Issue-1, October 2017 | Retrieval Number: A5181107117/17©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A major paradigm shift where power dissipation has become an important consideration as performance and area. RISC is termed as Reduced Instruction Set Computer, computer arithmetic-logic unit that uses a minimal instruction set, emphasizing the instructions used most often and optimizing them for the fastest possible execution In this work, a 64 bit RISC processor is presented with higher performance and efficiency being the main aim. This processor comprises of Control unit, general purpose registers, Arithmetic and logical unit, shift registers. Control unit follows instruction cycle of 3 stages fetch, decode and execute cycle. According to the instruction to the fetch stage, control unit generate signal to decode the instruction. The architecture supports 16 instructions for arithmetic, logical, shifting and rotational operations.
Keywords: RISC, Control Unit, ALU, Shift Register, Instruction Cycle
Scope of the Article: Design Engineering