An Efficient Methodology for Mapping Algorithms to Scalable Embedded Architectures
Ayman Elnaggar1, Mokhtar Aboelaze2
1Ayman Elnaggar, Department of Computer Science & Engineering, German University in Cairo, Canada.
2Mokhtar Aboelaze, Department of Computer Science, York University, Toronto, Canada.
Manuscript received on November 18, 2012. | Revised Manuscript received on December 20, 2012. | Manuscript published on December 30, 2012. | PP: 369-372 | Volume-2, Issue-2, December 2012. | Retrieval Number: B0921112212 /2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a general approach for generating higher order (longer size) multidimensional (m-d) architectures from m 2 lower order (shorter sizes) architectures. The objective of our work is to derive a unified framework and a design methodology that allows direct mapping of the proposed algorithms into embedded reconfigurable architectures such as FPGAs. Our methodology is based on manipulating tensor product forms so that they can be mapped directly into modular parallel architectures. The resulting circuits have very simple modular structure and regular topology.
Keywords: Reconfigurable Architectures, Recursive algorithms, multidimensional transforms, tensor products, permutation matrices.