Design of a Novel Economic Multiplier in VLSI using Reversible Logic Gates
Koushik Majumder1, Malay Kumar Pandit2, Asim Kumar Jana3
1Koushik Majumder, Electronics & Comm. Engg. Haldia Institute Of Technology, Haldia, East Midnapore, India.
2Prof.(Dr.) Malay K. Pandit, Electronics & Comm. Engg. Haldia Institute Of Technology, Haldia, East Midnapore, India.
3Asim K. Jana, Electronics & Comm. Engg. Haldia Institute Of Technology, Haldia, East Midnapore, India.
Manuscript received on November 19, 2012. | Revised Manuscript received on December 20, 2012. | Manuscript published on December 30, 2012. | PP: 317-321 | Volume-2, Issue-2, December 2012. | Retrieval Number: B0953112212 /2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we present a new architecture for multiplication in VLSI (Very Large Scale Integration) with the advantage of less quantum cost as well as less transistor count as a result of reduction in number of gates to improve power consumption. Classical Logic Gates such as AND, OR, NAND (Except NOT) gates are not reversible that is inputs cannot be recovered from the output. On the other hand, in Reversible Logic Gates inputs can be recovered completely from the output that is there is one to one mapping between inputs and outputs. Reversible logic gates use less power compared to classical gates and under ideal condition, they consume zero power. So we have designed a new architecture for multiplication using some reversible logic gates – BVF gate and Peres Gate. This helped us to achieve 24% less quantum cost, 15% less garbage output, and 23% less no. of gates, which effectively reduces no. of transistors, and hence power consumption is minimum.
Keywords: Adder, Garbage Output, Multiplier, Quantum Cost, Reversible Logic, VLSI.