Implementation of CMOS SRAM Cells in 7, 8, 10 and12-Transistor Topologies and their Performance Comparison
T. Santosh Kumar1, Suman Lata Tripathi2
1T. Santosh Kumar, Assistant Professor, Department of ECE, CMR Institute of Technology, Hyderabad (Telangana), India.
2Dr. Suman Lata Tripathi, Associate Professor, Department of ECE, Lovely Professional University, (Punjab), India.
Manuscript received on 22 April 2019 | Revised Manuscript received on 01 May 2019 | Manuscript Published on 05 May 2019 | PP: 227-229 | Volume-8 Issue-2S2, May 2019 | Retrieval Number: B10480182S219/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Memory is the important part of most of the electronic systems but the major problem with the design of memories is performance of devices i.e. speed and power dissipation. In this paper performance for read, write operations of SRAM cells based on different configurations are compared, specifically in each cell design the static-noise-margin (SNM) is calculated by observing butterfly characteristic curves. According to the result analysis the 7T SRAM cell in 45nm CMOS technology has less power dissipation and power delay product since it uses single bit for both read and write operations. The total circuitry is designed and simulated by using Cadence virtuoso and spectre respectively.
Keywords: CMOS, Power Product Delay, SRAM, SNM.
Scope of the Article: High Performance Computing