Energy Efficient Instruction Register for Green Communication
Shah Md Tanvir Siddiquee1, Keshav Kumar2, Bishwajeet Pandey3, Abhishek Kumar4
1Shah Md Tanvir Siddiquee, Daffodil International University, Bangladesh.
2Keshav Kumar, Chitkara University Institute of Engineering and Technology, Chitkara University, (Punjab), India.
3Bishwajeet Pandey, Center of Energy Excellence, Gyancity Research Lab, Motihari India.
4Abhishek Kumar, Center of Energy Excellence, Gyancity Research Lab, Motihari India.
Manuscript received on 22 April 2019 | Revised Manuscript received on 01 May 2019 | Manuscript Published on 05 May 2019 | PP: 312-314 | Volume-8 Issue-2S2, May 2019 | Retrieval Number: B10650182S219/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Our work represents the interfacing of instruction register with FPGA. In this work we have taken three different FPGA of Virtex family that are Virtex 4, Virtex 5 and Virtex 6 and have observed the power variation of instruction register with this three FPGA. This experiment is done on a Xilinx 14.1 ISE design suite. And the power of instruction register with three FPGA is analyzed with an X Power tool. All the other chips power which is implanted on instruction register counts zero in total, dynamic and quiescent power consumption. In this experiment, only one LUT flip flop pair is used. On comparing the power of instruction register with the three FPGA of Virtex family, we concluded that 90 nm Virtex-4 FPGA requires the least power among all the three FPGA.
Keywords: Instruction Register, FPGA, Virtex-4, Virtex-5, Virtex-6, Power Analysis.
Scope of the Article: Multimedia Communications