Design and Comparative Analysis of Conventional Adder and Pipelined Adder
Anjana Bhardwaj1, Swati Gupta2
1Anjana Bhardwaj, Asst. Professor, Dept. of ECE ABES Engineering College, Ghaziabad, India.
2Swati Gupta, M. Tech Scholar, Dept. of ECE Amity University, Noida, India.
Manuscript received on November 28, 2013. | Revised Manuscript received on December 12, 2013. | Manuscript published on December 30, 2013. | PP: 185-188 | Volume-3, Issue-2, December 2013. | Retrieval Number: B2415123213/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Adding two binary numbers is a basic operation in binany electronic processing system. Pipelining digital systems has been shown to provide significant performance gains over non-pipelined systems and remains a standard in microprocessor design. The desire for increased performance has seen a push for pipelines. Pipelining is considered to be a good technique for increasing the circuit speed. In this paper, 4-bit conventional adder and 4-bit pipelined adder has been implemented using Cadence virtuoso tool and simulation was performed using the generic 0.18 µm CMOS Technology at 5V. For comparison purposes, various parameters such as delay time, rise time and fall time has been compared which shows that pipelined adders are more efficient in terms of speed, power and throughput.
Keywords: Pipelining, Full Adder, Binary Adder.