A Proposed Cascaded Multilevel Inverter with R-Load at Different Carrier Frequencies
Lipika Nanda1, Aryadhara Pradhan2
1Lipika Nanda*, School of Electrical Engineering, KIIT Deemed to be University, Bhubaneswar, India.
2Aryadhara Pradhan, School of Electrical Engineering, KIIT Deemed to be University, Bhubaneswar, India.
Manuscript received on November 22, 2019. | Revised Manuscript received on December 15, 2019. | Manuscript published on December 30, 2019. | PP: 2650-2654 | Volume-9 Issue-2, December, 2019. | Retrieval Number: B4209129219/2019©BEIESP | DOI: 10.35940/ijeat.B4209.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Cascaded multilevel inverter has the major problem as voltage imbalance across the capacitors connected in circuits which are acting like dc sources. The number of level generation depends on the number of DC sources and switches placed in cascaded multilevel inverter topology. In this proposed topology the positive levels and zero levels of the inverter have been explained. This topology also work in symmetrical condition. The topology is simulated in MATLAB and its THDs are calculated at different modulation index. The voltage stress and loss calculations are carried out at different carrier frequencies.
Keywords: THD, Switching loss, Reduced device count, Modulation index.