Enhancing the Performance of Multilevel Inverters using Modified SVPWM Techniques
Ch. Lokeshwar Reddy1, G. Janardhan2
1Dr. Ch. Lokeshwar Reddy, Professor, Department of EEE, CVR College of Engineering, Hyderabad, India.
2Mr. J. Janardhan, Assistant Professor, Department of EEE, CVR College of Engineering, Hyderabad, India.
Manuscript received on January 23, 2020. | Revised Manuscript received on February 05, 2020. | Manuscript published on February 30, 2020. | PP: 3515-3521 | Volume-9 Issue-3, February 2020. | Retrieval Number: B4402129219/2020©BEIESP | DOI: 10.35940/ijeat.B4402.029320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, two types seven-level multilevel inverters in three phase configuration, Cascaded H-bridge Multilevel Inverter (CMLI) and Diode Clamped Multilevel Inverter (DCMLI) are simulated and compared the results for three different carrier PWM techniques. Here, Carrier based Sinusoidal Pulse Width Modulation (SPWM), Third Harmonic Injected Pulse Width Modulation (THIPWM) and Modified Carrier-Based Space Vector Pulse Width Modulation (SVPWM) are used as modulation strategies. These modulation strategies include Phase Disposition technique (PD), Phase Opposition Disposition technique (POD), and Alternate Phase Opposition Disposition technique (APOD). In all the modulation strategies, triangular carrier and trapezoidal triangular carrier signals are compared with reference signal for generation of control pulses. The simulations have been carried out for seven-level CMLI and DCMLI using MATLAB/Simulink. The detailed analysis of results in terms of %THD and utilization of DC-link voltage has been presented in this paper. By increasing the performance of inverters the utilization of input energy is reduced, then the corresponding energy sources can be reduced.
Keywords: Cascaded MLI, DCMLI, PDSVPWM, PODSVPWM.