A Suggestive Low Power TIQ Comparator Architecture using Adiabatic Logic for Implementation of 3-bit Flash type ADC.
Vishal Moyal
Vishal Moyal*, Department of Electrical Engineering, SVKM’s Institute of Technology, Dhule, (MS), India.
Manuscript received on November 24, 2019. | Revised Manuscript received on December 15, 2019. | Manuscript published on December 30, 2019. | PP: 5217-5221 | Volume-9 Issue-2, December, 2019. | Retrieval Number: B4416129219/2019©BEIESP | DOI: 10.35940/ijeat.B4416.129219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Power consumption is prime concern for the designers in modern day scenario. For the devices that are power-driven by tiny rechargeable or non-rechargeable batteries over the entire life period, such as medical transplant devices or portable medical instruments, necessitates lowest possible power consumption. In these devices Analog-to-Digital Converter (ADC) is dynamic component to provide connection amongst Analog and Digital system. The paper is aimed to report the design contests and tactics for low power ADCs which are used in biomedical graft devices and instruments. A comparator module of ADCs used in designing of such devices requires more power than other blocks in the device, a low power comparator is suggested for Threshold-Inverter-Quantizer (TIQ)using Diode-Free-Adiabatic-Logic (DFAL) to implement Flash type ADCs. The projected 3-bit Flash ADC is simulated using Cadence ® Virtuoso IC616 with TSMC 65nm technology. The ADC was simulated at peak to peak voltage of 1.2V and capacitive load of 1fF,results in consumption of5.53 µW of average power, which is 66.03 % lesser relative tocon servative CMOS-TIQ based comparator. Observed static parameters are: DNL is equal to-0.62 / + 0.57 LSB and INL is equal to- 0.44/ +0.41 LSB. Dynamic parameters observed results are as: THD = -25.25dB, SNR=19.45 dB, SNDR=18.39 dB, ENOB=2.76 bits, SFDR = 23.4 dB.
Keywords: CMOS, PMOS, NMOS, ADC, TIQ,DFAL, VTC, MUX, LSB, DNL, INL, SFDR,SNR, ENOB.