Round Rescheduling Technique for Hash Function Blake using Carry Select Adder with Binary to Excess Converter
S.Jananee1, N.Annu2, K.Jayapriyadharshini3
1S. Jananee, Electronics and Communication Engineering, Avinashilingam Institute for Home Science and Higher Education for Women University, Coimbatore, India.
2N.Annu, Electronics and Communication Engineering, Avinashilingam Institute for Home Science and Higher Education for Women University, Coimbatore, India.
3K.Jayapriyadharshini, Electrical and Electronics Engineering, Annamalai University, Coimbatore, India.
Manuscript received on January 23, 2013. | Revised Manuscript received on February 10, 2013. | Manuscript published on February 28, 2013. | PP: 115-119 | Volume-2 Issue-3, February 2013. | Retrieval Number: C1033022313 /2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Cryptographic hash functions are used widely in many applications mainly for its high speed and security. NIST organized SHA-3 competition and the final round candidates are BLAKE, KECCAK, SKEIN, JH AND GROSTL. Among the five finalists design and architecture of BLAKE is analyzed in this paper. Hash function BLAKE is the one-way cryptography which means no key is used while sending and receiving the message. In the field of cryptography speed and secrecy are the tradeoffs. To obtain high speed and efficiency, Round Rescheduling Technique is incorporated. To make BLAKE more efficient, modular addition is replaced with Carry Select Adders (CSA) using Binary to Excess Converter (BEC). The Existing and Proposed architecture of BLAKE is designed using CSA whereas Modified BLAKE is designed using CSA with BEC. So that the Area and Power consumed in Proposed method is less compared with Existing methods. BLAKE-32 and BLAKE-64 are coded in VHDL language and simulated in Mentor Graphics Front-End tool – Modelsim. Area and Power results are shown in Xilinx ISE simulator.
Keywords: Hash Function, SHA-3, NIST CSA, BEC, VHDL, Xilinx ISE simulator.