A Two-Pass Assembler for the AMIR CPU Microprocessor
M.N. Ibrahim1, M.Idroas2, J.Kassim N. Azhari3, A. Baharum E.B.L. Eline4
1M.N. Ibrahim, Department of Engineering, Universiti, Teknologi Malaysia.
2M.Idroas, Department of Engineering, Universiti Teknologi Malaysia.
3J.Kassim N. Azhari, Department of Engineering, Universiti, Teknologi Malaysia.
4A.Baharum E.B.L. Eline, Department of Engineering, Universiti, Teknologi Malaysia.
Manuscript received on 29 May 2019 | Revised Manuscript received on 11 June 2019 | Manuscript Published on 22 June 2019 | PP: 498-500 | Volume-8 Issue-3S, February 2019 | Retrieval Number: C11050283S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Today’s demands for high performance computing on embedded devices call for high performance microprocessor. There are two families of most popular microprocessors namely Intel and ARM. However, these microprocessors have lots of limitations due to their architectures, which are inherited from older versions. The results are their assembly language become too complicated to be used for writing useful applications, hence high level languages were promoted, which is inefficient for hardware access. The AMIR CPU, which was developed at the Advanced Microprocessor Research Laboratory, Universiti Teknologi Malaysia was designed after careful study of weaknesses of present microproceesors both in terms of hardware architecture Instruction Set. A new two-pass assembler was developed to convert the AMIR CPU assembly language to its corresponding machine codes. A few application programs were written and successfully tested working on a DE0 FPGA board containing the AMIR CPU.
Keywords: AMIR CPU, Microprocessor, Two-Pass Assembler, FPGA.
Scope of the Article: FPGAs