Design and Simulation of 16 Bit Arithmetic Unit using Gating Techniques in Cadence 45nm Technology
K. Bikshalu1, Prathap Soma2
1Dr. K. Bikshalu, Department of Electronics and Communication Engineering, University College of Engineering, Kakatiya University, Kothagudem (Telangana). India.
2Prathap Soma, Asst. Prof., Department of Electronics and Communication Engineering, CVR College of Engineering, Hyderabad (Telangana). India.
Manuscript received on 15 February 2017 | Revised Manuscript received on 22 February 2017 | Manuscript Published on 28 February 2017 | PP: 218-223 | Volume-6 Issue-3, February 2017 | Retrieval Number: C4857026317/17©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In any system ALU is the most important part of a processor as it is required for calculating the address of each memory location. It performs a particular arithmetic and logic operations on each set of operands, based upon the instructions given by the processor. In some processors ALU is split into two units, an Arithmetic unit (AU) and logic unit (LU). Some processors possess a couple of Arithmetic units – one for the fixed point operations and another for the floating point operations. As AU operates at a very high speed and it is accessed by the system frequently, it contributes to one of the highest power-density locations on the processor. Because of this reason, there exist thermal hotspots and sharp temperature gradients inside the execution core, thereby reducing the reliability as well as the battery life of the system. Therefore, there is a great need for the development of a power optimized AU design. This encourages powerfully for the design of a power optimized AU that satisfies the superior needs along with the reduction of average power consumption. This paper presents the various power optimized techniques for 16bit ALU like input gating, power gating in 45nm using cadence. Finally, comparison among all proposed techniques are represented.
Keywords: Arithmetic Unit (AU), Power Gating, Input Gating.
Scope of the Article: Design Optimization of Structures