Pipelined Floating-Point Arithmetic Unit (FPU) for Advanced Computing Systems using FPGA
Rathindra Nath Giri1, M. K. Pandit2
1Rathindra Nath Giri, Department of electronics and communication engineeringe, Haldia Institute of technology, Haldia, India.
2Prof.(Dr.)Malay Kumar Pandit, Dean of school of engineering and professor of electronics and communication engineering, Haldia Institute of technology, Haldia, India.
Manuscript received on March 12, 2012. | Revised Manuscript received on April 22, 2012. | Manuscript published on Apirl 30, 2012. | PP: 168-174 | Volume-1 Issue-4, April 2012 | Retrieval Number: D0331041412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Field Programmable Gate Arrays (FPGA) are increasingly being used to design high-end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. An efficient design of floating-point adder onto an FPGA offers major area and performance overheads. With the recent advancement in FPGA architecture and area density, latency has been the main focus of attention in order to improve performance. Our research was oriented towards studying and implementing standard .Our work is an important design resource for development of floating-point adder hardware on FPGAs. This article reports the work done on the design of control path and data path of an optimized 64bit floating-point addition operation using field programmable gate array. At first we selected carry skip adder logic due to its best performance in terms of area, speed and power then we employ common a graph to determine the best mix of cutsets, registors, MUXs for pipelining.
Keywords: Data path, control path, VLSI, FPGA, adder logic, floating point addition, optimization, pipelining.