FPGA Design Flow for SDR Transceiver using System Generator
Tahseen Flaih Hasan
Tahseen Flaih Hasan, Foundation of Technical Education, Baghdad, Iraq.
Manuscript received on March 22, 2014. | Revised Manuscript received on April 17, 2014. | Manuscript published on April 30, 2014. | PP: 252-258 | Volume-3, Issue-4, April 2014. | Retrieval Number: D2816043414/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Software defined radio (SDR) is highly configurable hardware platform that provides technology for realizing the rapidly expanding third (even future) generation digital wireless communication infrastructure. While among the silicon alternatives available for implementing the various functions of SDR, field programmable gate array (FPGA) is an attractive option in terms of performance, power consumption, and flexibility. This paper examines 16-QAM (Quadrature Amplitude Modulation) SDR transmitter and receiver with an appropriate timing recovery system using FPGA. We provide a tutorial style overview of techniques and schemes for system (abstraction) level design of the 16-QAM SDR transmitter and receiver using Xilinx System Generator, ModelSim and Synplify Pro software, and FPGA implementation (realization) using Xilinx ISE software. Two design alternatives are presented to highlight the rich design space accessible using the FPGA configurable logic. At last, this new design technique would help in designing and realizing SDR to 3G wireless communication system and accelerate the transition to 4G wireless communication system.
Keywords: FPGA, 16QAM, SDR, System Generator.