Leakage Power Optimization for VLSI Circuits @90nm CMOS Process
A. Mathumathi1, Nivya. R. Mohan2, Neethu Babu3, D. Padmapriya4, Anoop5, M. Geetha Priya6
1A. Mathumathi, is Currently Doing B. Tech Degree in Electronics and Communication Engineering in Amrita Vishwa Vidyapeetham, Coimbatore, India.
2Nivya. R .Mohan, is Currently Doing B. Tech Degree in Electronics and Communication Engineering in Amrita Vishwa Vidyapeetham, Coimbatore, India.
3Neethu Babu, is Currently Doing B. Tech Degree in Electronics and Communication Engineering in Amrita Vishwa Vidyapeetham, Coimbatore, India.
4D. Padmapriya, is Currently Doing B. Tech Degree in Electronics and Communication Engineering in Amrita Vishwa Vidyapeetham, Coimbatore, India.
5Anoop, is Currently Doing B. Tech Degree in Electronics and Communication Engineering in Amrita Vishwa Vidyapeetham, Coimbatore, India.
6M.Geetha Priya, B.E. Degree in Electronics and Communication Engineering from Anna University, Coimbatore, India.
Manuscript received on March 12, 2014. | Revised Manuscript received on April 03, 2014. | Manuscript published on April 30, 2014. | PP: 69-72 | Volume-3, Issue-4, April 2014. | Retrieval Number: D2818043414/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In Integrated Circuits (IC), the transistor density is increased by scaling down the size of MOSFETs. Scaling down of devices sizes for improving the performance has lead to a substantial increase in the subthreshold leakage current. In this paper, a new method is proposed to reduce leakage power in standby mode of operation. This proposed method combines Input Vector Control (IVC) and Gate Replacement (GR) techniques. The proposed method is validated by applying to three different benchmark circuits at 90nm CMOS process technology using HSPICE. The final results obtained are compared with other well known leakage reduction techniques and the proposed method proves to be more effective than other existing techniques.
Keywords: Leakage reduction, HSPICE, CMOS, Full adder, PDP.