Design and Analysis of Conventional CMOS and Energy Efficient Adiabatic Logic for Low Power VLSI Application
Anamika Mishra1, Anju Jaiswal2, Ankita Jaiswal3, A.K.Niketa4
1Anamika Mishra, Department of Electronics and Communication Engg, Ram Swaroop Engineering College, Lucknow, India.
2Dr. Anju Jaiswal, Department of Electronics and Communication Engg, Ram Swaroop Engineering College, Lucknow, India.
3Ankita Jaiswal, Department of Electronics and Communication Engg, Ram Swaroop Engineering College, Lucknow, India.
4A.K. Niketa, Department of Electronics and Communication Engg., Ram Swaroop Engineering College, Lucknow, India.
Manuscript received on May 01, 2014. | Revised Manuscript received on May 14, 2014. | Manuscript published on April 30, 2014. | PP: 295-299 | Volume-3, Issue-4, April 2014. | Retrieval Number: D2994043414/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In recent years, low power circuit design has been an important issue in VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. energy. This paper proposes an Adder circuit based on energy efficient two-phase clocked adiabatic logic. A simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and hence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL) and Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison has shown a significant power saving to the extent of 70% in case of proposed technique as compared to CMOS logic in 10 to 200MHz transition frequency range. Comparative results has also been shown by a histogram which represents the least power dissipation of proposed technique. In this paper all circuits are analyzed in terms of power using 0.35um technology and simulated using Pspice.
Keywords: Adiabatic logic, Energy recovery, Power supply, low power, Full adder, Positive feedback adiabatic logic, 2PASCL.