A Novel Symmetrical Multilevel Inverter with Reduced Switch Count Ujwala Gajula 
Ujwala Gajula
Ujwala Gajula*, Assistant Professor, EEE Department, G.N.I.T.S, India.
Manuscript received on March 28, 2020. | Revised Manuscript received on April 25, 2020. | Manuscript published on April 30, 2020. | PP: 1651-1656 | Volume-9 Issue-4, April 2020. | Retrieval Number: D7964049420/2020©BEIESP | DOI: 10.35940/ijeat.D7964.049420
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Abstract: Multilevel inverters produced lot of interest in academia and industry as they are becoming feasible technology for number of applications. These are considered as the progressing power converter topologies. To generate a quality output waveform with minimum number of switches, reduced switch multilevel inverter topologies has come in focus. This paper introduces a modified symmetrical MLI with reduced component count thereby ensuring the minimum switching losses, reduced total harmonic distortion, Size and installation cost. By proper combination of switches it produces a staircase output waveform with low harmonic distortion. In this paper novel symmetrical inverter topology with reduced component count based on level shift phase opposition and disposition PWM (PODPWM) is proposed. The results are validated using MATLAB/SIMULINK.
Keywords: Reduced switch MLI, Level shift pulse width modulation, Switching losses, Total Harmonic distortion, Staircase output Waveform.