Design of High Speed FFT using Urdhva-Tiryagbhyam Algorithm and Karatsuba Algorithm
S. S. Kerur1, Mustaq Kunnur2
1Dr. S. S. Kerur*, Assistant Professor, Department of Electronics and Communication Engineering at SDM College of Engineering and Technology, Dharwad, Karnataka, India.
2Mr. Mustaq Kunnur, M.Tech student, Department of Electronics and Communication Engineering at SDM College of Engineering and Technology, Dharwad, Karnataka, India
Manuscript received on March 28, 2020. | Revised Manuscript received on April 25, 2020. | Manuscript published on April 30, 2020. | PP: 1904-1908 | Volume-9 Issue-4, April 2020. | Retrieval Number: D8783049420/2020©BEIESP | DOI: 10.35940/ijeat.D8783.049420
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Abstract: In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.
Keywords: Fast Fourier Transform, Urdhva Tiryagbhyam algorithm, Karatsuba algorithm, IEEE 754 single preciseness floating point multiplier, booth multiplier.